With rapid development of integrated circuit technology, the feature size of a CMOS device is continuously reduced both in a longitudinal direction and in a lateral direction. A gate dielectric needs to have a thickness smaller than 8 angstroms, or even smaller than 6 angstroms, which is equivalent to a thickness of 2-3 atomic layers, so as to suppress short channel effects due to the reduced size. A gate tunneling current increases remarkably in exponential relation to the thickness of the gate dielectric. Consequently, the device does not function properly. A high-K gate dielectric has a larger physical thickness than a conventional gate dielectric such as SiO2 with the same gate capacitance, and may be used for replacing the latter to decrease the gate tunneling leakage current remarkably. However, a conventional polysilicon gate is incompatible with the high-K gate dielectric and causes severe Fermi pinning effect, and needs also to be replaced by a novel metal gate. The metal gate not only eliminates a depletion effect of the polysilicon gate to decrease a gate resistance, but also eliminates boron penetration to improve reliability of the device. A gate dielectric having a high dielectric constant (K) and a metal gate represent a tendency of development in advanced technology of the high-performance nano-integrated circuit. However, there are many challenges in the integrated implementation of the metal gate with the high-K dielectric, such as thermal stability and interfacial state. Particularly, the Fermi pinning effect is big challenge for achieving the desired low threshold voltage of the nano-CMOS device, especially in a gate-first process. To achieve the desired low threshold voltage of the nano-CMOS device, an effective work function of an NMOS device should be near a bottom of a conduction band of Si, i.e. about 4.1 eV, and an effective work function of a PMOS device should be near a top of a valence band of Si, i.e. about 5.2 eV. Thus, the NMOS device and the PMOS device typically require different metal gates and high-K dielectrics suitable for the two types of devices respectively. It would therefore be desirable to provide the integration implementation of double metal gates and double high-K dielectrics to fulfill the requirement of the high-performance CMOS device under 45 nm/32 nm/22 nm technical node and beyond.